An ultra-low power CMOS random number generator

This paper proposes an ultra-low power CMOS random number generator (RNG), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 lm CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 lW. This novel circuit is a promising unit for low power system and communication applications. 2007 Elsevier Ltd. All rights reserved.